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hn58c256a series hn58c257a series 256k eeprom (32-kword 8-bit) ready/ busy and res function (hn58c257a) ade-203-410d (z) rev. 4.0 oct. 24, 1997 description the hitachi hn58c256a and hn58c257a are electrically erasable and programmable roms organized as 32768-word 8-bit. they have realized high speed low power consumption and high reliability by employing advanced mnos memory technology and cmos process and circuitry technology. they also have a 64-byte page programming function to make their write operations faster. features single 5 v supply: 5 v ?0% access time: 85 ns/100 ns (max) power dissipation ? active: 20 mw/mhz, (typ) ? standby: 110 w (max) on-chip latches: address, data, ce , oe , we automatic byte write: 10 ms max automatic page write (64 bytes): 10 ms max ready/ busy (only the hn58c257a series) data polling and toggle bit data protection circuit on power on/off conforms to jedec byte-wide standard reliable cmos with mnos cell technology 10 5 erase/write cycles (in page mode) 10 years data retention software data protection write protection by res pin (only the hn58c257a series) industrial versions (temperatur range: ?20 to 85?c and ?40 to 85?c) are also available.
hn58c256a series, hn58c257a series 2 ordering information type no. access time package HN58C256AP-85 HN58C256AP-10 85 ns 100 ns 600 mil 28-pin plastic dip (dp-28) hn58c256afp-85 hn58c256afp-10 85 ns 100 ns 400 mil 28-pin plastic sop (fp-28d) hn58c256at-85 hn58c256at-10 85 ns 100 ns 28-pin plastic tsop (tfp-28db) hn58c257at-85 hn58c257at-10 85 ns 100 ns 8 14 mm 2 32-pin plastic tsop (tfp-32da) pin arrangement HN58C256AP/afp series hn58c256at series hn58c257at series (top view) (top view) (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss v cc we a13 a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 a2 a1 a0 i/o0 i/o1 i/o2 v ss i/o3 i/o4 i/o5 i/o6 i/o7 ce a10 a3 a4 a5 a6 a7 a12 a14 v cc we a13 a8 a9 a11 oe 15 16 17 18 19 20 21 22 23 24 25 26 27 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a2 a1 a0 i/o0 i/o1 i/o2 v ss i/o3 i/o4 i/o5 i/o6 i/o7 ce a10 a3 a4 a5 a6 a7 a12 a14 v cc we a13 a8 a9 a11 oe 17 18 19 20 21 22 23 24 25 26 27 28 29 30 16 15 14 13 12 11 10 9 8 7 6 5 4 3 31 32 2 1 nc nc res rdy/ busy
hn58c256a series, hn58c257a series 3 pin description pin name function a0 to a14 address input i/o0 to i/o7 data input/output oe output enable ce chip enable we write enable v cc power supply v ss ground rdy/ busy * 1 ready busy res * 1 reset nc no connection note: 1. this function is supported by only the hn58c257a series. block diagram note: this function is supported by only the hn58c257a series. v v oe ce a5 a0 a6 a14 we cc ss i/o0 i/o7 high voltage generator control logic and timing y decoder x decoder address buffer and latch i/o buffer and input latch y gating memory array data latch res rdy/ busy res * 1 * 1 * 1 to to to
hn58c256a series, hn58c257a series 4 operation table operation ce oe we res * 3 rdy/ busy * 3 i/o read v il v il v ih v h * 1 high-z dout standby v ih * 2 high-z high-z write v il v ih v il v h high-z to v ol din deselect v il v ih v ih v h high-z high-z write inhibit v ih v il data polling v il v il v ih v h v ol dout (i/o7) program reset v il high-z high-z notes: 1. refer to the recommended dc operating condition. 2. : don? care 3. this function is supported by only the hn58c257a series. absolute maximum ratings parameter symbol value unit power supply voltage rerative to v ss v cc ?.6 to +7.0 v input voltage rerative to v ss vin ?.5* 1 to +7.0* 3 v operationg temperature range* 2 topr 0 to +70 c storage temperature range tstg ?5 to +125 c notes: 1. vin min = ?.0 v for pulse width 50 ns 2. including electrical characteristics and data retention 3. should not exceed v cc + 1 v.
hn58c256a series, hn58c257a series 5 recommended dc operating conditions parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v v ss 00 0v input voltage v il ?.3* 1 0.8 v v ih 2.2 v cc + 0.3* 2 v v h * 3 v cc ?0.5 v cc + 1.0 v operating temperature topr 0 70 c notes: 1. v il min: ?.0 v for pulse width 50 ns. 2. v ih max: v cc + 1.0 v for pulse width 50 ns. 3. this function is supported by only the hn58c257a series. dc characteristics (ta = 0 to +70c, v cc = 5.0 v?0%) parameter symbol min typ max unit test conditions input leakage current i li 2* 1 m av cc = 5.5 v, vin = 5.5 v output leakage current i lo 2 m av cc = 5.5 v, vout = 5.5/0.4 v standby v cc current i cc1 20 m a ce = v cc i cc2 1 ma ce = v ih operating v cc current i cc3 12 ma iout = 0 ma, duty = 100%, cycle = 1 m s at v cc = 5.5 v 30 ma iout = 0 ma, duty = 100%, cycle = 85 ns at v cc = 5.5 v output low voltage v ol 0.4 v i ol = 2.1 ma output high voltage v oh 2.4 v i oh = ?00 m a note: 1. i li on res = 100 m a max (only the hn58c257a series) capacitance (ta = +25c, f = 1 mhz) parameter symbol min typ max unit test conditions input capacitance* 1 cin 6 pf vin = 0 v output capacitance* 1 cout 12 pf vout = 0 v note: 1. this parameter is periodically sampled and not 100% tested.
hn58c256a series, hn58c257a series 6 ac characteristics (ta = 0 to +70c, v cc = 5 v?0%) test conditions input pulse levels: 0.4 v to 3.0 v 0 v to v cc ( res pin* 2 ) input rise and fall time: 5 ns input timing reference levels: 0.8, 2.0 v output load: 1ttl gate +100 pf output reference levels: 1.5 v, 1.5 v read cycle hn58c256a/hn58c257a -85 -10 parameter symbol min max min max unit test conditions address to output delay t acc 85 100 ns ce = oe = v il , we = v ih ce to output delay t ce 85 100 ns oe = v il , we = v ih oe to output delay t oe 10 40 10 50 ns ce = v il , we = v ih address to output hold t oh 00ns ce = oe = v il , we = v ih oe ( ce ) high to output float* 1 t df 0 40 0 40 ns ce = v il , we = v ih res low to output float* 1, 2 t dfr 0 350 0 350 ns ce = oe = v il , we = v ih res to output delay* 2 t rr 0 450 0 450 ns ce = oe = v il , we = v ih
hn58c256a series, hn58c257a series 7 write cycle parameter symbol min* 3 typ max unit test conditions address setup time t as 0 ns address hold time t ah 50ns ce to write setup time ( we controlled) t cs 0 ns ce hold time ( we controlled) t ch 0 ns we to write setup time ( ce controlled) t ws 0 ns we hold time ( ce controlled) t wh 0 ns oe to write setup time t oes 0 ns oe hold time t oeh 0 ns data setup time t ds 50ns data hold time t dh 0 ns we pulse width ( we controlled) t wp 100 ns ce pulse width ( ce controlled) t cw 100 ns data latch time t dl 50ns byte load cycle t blc 0.2 30 m s byte load window t bl 100 m s write cycle time t wc 10* 4 ms time to device busy t db 120 ns write start time t dw 0* 5 ns reset protect time* 2 t rp 100 m s reset high time* 2, 6 t res 1 m s notes: 1. t df and t dfr are defined as the time at which the outputs achieve the open circuit conditions and are no longer driven. 2. this function is supported by only the hn58c257a series. 3. use this device in longer cycle than this value. 4. t wc must be longer than this value unless polling techniques or rdy/ busy (only the hn58c257a series) are used. this device automatically completes the internal write operation within this value. 5. next read or write operation can be initiated after t dw if polling techniques or rdy/ busy (only the hn58c257a series) are used. 6. this parameter is sampled and not 100% tested. 7. a6 through a14 are page address and these addresses are latched at the first falling edge of we . 8. a6 through a14 are page address and these addresses are latched at the first falling edge of ce . 9. see ac read characteristics.
hn58c256a series, hn58c257a series 8 read timing waveform address ce oe we data out high data out valid t acc t ce t oe t oh t df t rr t dfr res * 2
hn58c256a series, hn58c257a series 9 byte write timing waveform (1) ( we controlled) address ce we oe din rdy/ busy * 2 t wc t ch t ah t cs t as t wp t oeh t bl t oes t ds t dh t db t rp res * 2 v cc t res high-z high-z t dw
hn58c256a series, hn58c257a series 10 byte write timing waveform (2) ( ce controlled) address ce we oe din rdy/ busy * 2 t wc t ah t ws t as t oeh t wh t oes t ds t dh t db t rp res * 2 v cc t cw t bl t dw t res high-z high-z
hn58c256a series, hn58c257a series 11 page write timing waveform (1) ( we controlled) address a0 to a14 we ce oe din rdy/ busy * 2 t as t ah t bl t wc t oeh t dh t db t oes t rp t res res * 2 v cc t ch t cs t wp t dl t blc t ds t dw high-z high-z *7
hn58c256a series, hn58c257a series 12 page write timing waveform (2) ( ce controlled) address a0 to a14 we ce oe din rdy/ busy * 2 t as t ah t bl t wc t oeh t dh t db t oes t rp t res res * 2 v cc t wh t ws t cw t dl t blc t ds t dw high-z high-z *8
hn58c256a series, hn58c257a series 13 data polling timing waveform t ce t oeh t wc t dw t oes address ce we oe i/o7 t oe din x an an dout x dout x *9 *9 an
hn58c256a series, hn58c257a series 14 toggle bit this device provide another function to determine the internal programming cycle. if the eeprom is set to read mode during the internal programming cycle, i/o6 will charge from ??to ??(toggling) for each read. when the internal programming cycle is finished, toggling of i/o6 will stop and the device can be accessible for next read or program. toggle bit waveform notes: 1. i/o6 beginning state is "1". 2. i/o6 ending state will vary. 3. see ac read characteristics. 4. any address location can be used, but the address must be fixed. we t oes oe ce dout i/o6 dout dout dout next mode t oe t ce t dw t wc t oeh *1 *2 *2 address *3 *3 *4 din
hn58c256a series, hn58c257a series 15 software data protection timing waveform (1) (in protection mode) v ce we address data 5555 aa 2aaa 55 5555 a0 t blc t wc cc write address write data software data protection timing waveform (2) (in non-protection mode) v ce we address data t wc cc normal active mode 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 20
hn58c256a series, hn58c257a series 16 functional description automatic page write page-mode write feature allows 1 to 64 bytes of data to be written into the eeprom in a single write cycle. following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. each additional byte load cycle must be started within 30 s from the preceding falling edge of we or ce . when ce or we is high for 100 s after data input, the eeprom enters write mode automatically and the input data are written into the eeprom. data polling data polling indicates the status that the eeprom is in a write cycle or not. if eeprom is set to read mode during a write cycle, an inversion of the last byte of data outputs from i/o7 to indicate that the eeprom is performing a write operation. rdy/ busy signal ( only the hn58c257a series ) rdy/ busy signal also allows status of the eeprom to be determined. the rdy/ busy signal has high impedance except in write cycle and is lowered to v ol after the first write signal. at the end of a write cycle, the rdy/ busy signal changes state to high impedance. res signal ( only the hn58c257a series ) when res is low, the eeprom cannot be read or programmed. therefore, data can be protected by keeping res low when v cc is switched. res should be high during read and programming because it doesn't provide a latch function. v program inhibit cc res program inhibit read inhibit read inhibit
hn58c256a series, hn58c257a series 17 we , ce pin operation during a write cycle, addresses are latched by the falling edge of we or ce , and data is latched by the rising edge of we or ce . write/erase endurance and data retention time the endurance is 10 5 cycles in case of the page programming and 10 4 cycles in case of the byte programming (1% cumulative failure rate). the data retention time is more than 10 years when a device is page- programmed less than 10 4 cycles. data protection 1. data protection against noise on control pins ( ce , oe , we ) during operation during readout or standby, noise on the control pins may act as a trigger and turn the eeprom to programming mode by mistake. to prevent this phenomenon, this device has a noise cancelation function that cuts noise if its width is 20 ns or less. be careful not to allow noise of a width of more than 20 ns on the control pins. we ce oe v 0 v v 0 v 20 ns max ih ih
hn58c256a series, hn58c257a series 18 2. data protection at v cc on/off when v cc is turned on or off, noise on the control pins generated by external circuits (cpu, etc) may act as a trigger and turn the eeprom to program mode by mistake. to prevent this unintentional programming, the eeprom must be kept in an unprogrammable state while the cpu is in an unstable state. note: the eeprom shoud be kept in unprogrammable state during v cc on/off by using cpu reset signal. v cc cpu reset unprogrammable unprogrammable * * (1) protection by ce , oe , we to realize the unprogrammable state, the input level of control pins must be held as shown in the table below. ce v cc oe v ss we v cc : don? care. v cc : pull-up to v cc level. v ss : pull-down to v ss level.
hn58c256a series, hn58c257a series 19 (2) protection by res (only the hn58c257a series) the unprogrammable state can be realized by that the cpu? reset signal inputs directly to the eeprom? res pin. res should be kept v ss level during v cc on/off. the eeprom breaks off programming operation when res becomes low, programming operation doesn? finish correctly in case that res falls low during programming operation. res should be kept high for 10 ms after the last data input. v cc res we or ce 100 s min 10 ms min 1 s min program inhibit program inhibit
hn58c256a series, hn58c257a series 20 3. software data protection to prevent unintentional programming, this device has the software data protection (sdp) mode. the sdp is enabled by inputting the following 3 bytes code and write data. sdp is not enabled if only the 3 bytes code is input. to program data in the sdp enable mode, 3 bytes code must be input before write data. data aa 55 a0 write data } address 5555 2aaa 5555 write address normal data input the sdp mode is disabled by inputting the following 6 bytes code. note that, if data is input in the sdp disable cycle, data can not be written. data aa 55 80 aa 55 20 address 5555 2aaa 5555 5555 2aaa 5555 the software data protection is not enabled at the shipment. note: there are some differences between hitachi? and other company? for enable/disable sequence of software data protection. if there are any questions , please contact with hitachi sales offices.
hn58c256a series, hn58c257a series 21 package dimensions HN58C256AP series (dp-28) 0.51 min 2.54 min 0.25 + 0.11 ?0.05 2.54 0.25 0.48 0.10 0 ?15 15.24 1.2 35.6 36.5 max 13.4 14.6 max 1 14 15 28 5.70 max 1.9 max hitachi code jedec eiaj weight (reference value) dp-28 conforms 4.6 g unit: mm
hn58c256a series, hn58c257a series 22 package dimensions (cont.) hn58c256afp series (fp-28d) 0 ?8 0.17 0.05 1.0 0.2 0.20 0.10 2.50 max 8.4 18.3 18.8 max 1.12 max 28 15 1 14 11.8 0.3 1.7 0.20 0.15 m 1.27 0.40 0.08 0.38 0.06 0.15 0.04 hitachi code jedec eiaj weight (reference value) fp-28d conforms 0.7 g unit: mm dimension including the plating thickness base material dimension
hn58c256a series, hn58c257a series 23 package dimensions (cont.) hn58c256at series (tfp-28db) 0.10 m 0.55 8.00 0.22 0.08 13.40 0.30 0.17 0.05 0.13 1.20 max 11.80 0 ?5 28 1 14 15 8.20 max 0.10 +0.07 ?.08 0.50 0.10 0.80 0.45 max hitachi code jedec eiaj weight (reference value) tfp-28db 0.23 g 0.20 0.06 0.15 0.04 unit: mm dimension including the plating thickness base material dimension
hn58c256a series, hn58c257a series 24 package dimensions (cont.) hn58c257at series (tfp-32da) hitachi code jedec eiaj weight (reference value) tfp-32da conforms conforms 0.26 g 0.10 0.08 m 0.50 8.00 0.22 0.08 14.00 0.20 1.20 max 12.40 32 116 17 0.17 0.05 0.13 0.05 0 ?5 8.20 max 0.45 max 0.50 0.10 0.80 0.20 0.06 0.125 0.04 unit: mm dimension including the plating thickness base material dimension
hn58c256a series, hn58c257a series 25 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachi? permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user? unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachi? semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachi? products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachi? sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachi? products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi america, ltd. semiconductor & ic div. 2000 sierra point parkway brisbane, ca. 94005-1835 u s a tel: 415-589-8300 fax: 415-583-4207 hitachi europe gmbh electronic components group continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30 00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 0628-585000 fax: 0628-778322 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 0104 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071

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